Flash memory has become widely used as a storage medium for a variety of applications. Flash memory uses electrically-erasable programmable read-only memory (EEPROM) as the non-volatile storage. For example, flash-memory cards can store digital pictures and video from a digital camera and transfer these pictures to a personal computer (PC). The flash-memory card is removed from the digital camera and inserted into a flash-memory reader attached to (or part of) the PC to transfer the pictures. Personal digital assistant (PDA's), music players, and other devices may also use flash-memory cards in a similar way.
A flash-card reader may be a stand-alone device that attaches to the PC using a Universal-Serial-Bus (USB), IEEE 1394, Integrated Device Electronics (IDE), serial AT-attachment (SATA), or other interface.
FIG. 1 shows a prior-art flash drive. Flash-memory controller 20 reads or writes flash memory 8 that is a permanent or removable part of flash drive controller device 61. CPU 10 executes routines stored in ROM 12 that include routines to send commands to flash-memory controller 20 to read and write the flash memory. CPU 10 also controls serial engine 22, which transfers data serially over USB link 18.
CPU 10 may use scratch-pad RAM 14 to store parameters, execution states, or small amounts of data being re-formatted during a transfer, but large amounts of the flash data being transferred is not normally stored in scratch-pad RAM 14. Data is normally transferred word-by-word directly from flash-memory controller 20 to CPU 10 and then to serial engine 22 without storage in scratch-pad RAM 14. New data words over-write any pervious data words, allowing scratch-pad RAM 14 to have a small capacity.
Data transfer rates are limited by bus 16. Bus 16 is a CPU-controlled bus. Master port 15 on CPU 10 acts as a bus master, controlling data transfer to and from one of slave ports 11, 17, 21, 23 on ROM 12, scratch-pad RAM 14, flash-memory controller 20, and serial engine 22, respectively.
FIG. 2 shows a prior-art flash-card reader. Flash-card controllers 24, 26 read or write flash memory on flash cards inserted into slots A, B of flash-card reader controller device 63. CPU 10 executes routines stored in ROM 12 that include routines to send commands to flash-card controllers 24, 26 to read and write the flash memory. CPU 10 also controls serial engine 22, which transfers data serially over USB link 18.
Data is normally transferred byte-by-byte directly from flash-card controllers 24, 26 to CPU 10 and then to serial engine 22 without storage in scratch-pad RAM 14. The width of bus 16 is often 8-bits (byte), but can be wider, and multiples of bus 16, such as 4, 8, or more burst transfers can occur.
Unfortunately, data-transfer rates may be limited by bus 16. Bus 16 is a CPU-controlled bus. Master port 15 on CPU 10 acts as a bus master, controlling data transfer to and from one of slave ports 11, 17, 23, 25, 27 on ROM 12, scratch-pad RAM 14, serial engine 22, and flash-card controllers 24, 26, respectively.
FIG. 3 shows a prior art PC with a USB interface. The flash drive/reader of FIGS. 1, 2 can be connected to USB link 128 of the PC in FIG. 3. CPU 104 executes programs for the user or operating system, using code in ROM 106 or in synchronous dynamic-random-access memory (SDRAM) 102. CPU 104 uses master port 105 to access SDRAM 102 through north bridge 108, which is an interface chip.
When transferring data such as a music file over USB link 128 to a flash card in an external reader, CPU 104 writes a data structure (from the music file, for example) in SDRAM 102. Then CPU 104 sends commands to USB host controller 122. CPU 104 uses its master port 105 to send the commands through north bridge 108 over Peripheral Component Interconnect (PCI) bus 120 to USB host controller 122. Master-slave port 123 on USB host controller 122 acts as a slave to receive these commands.
Once the commands are received by USB host controller 122, master-slave port 123 acts as a master of PCI bus 120. USB host controller 122 goes over PCI bus 120 and through north bridge 108 to read the data structure in SDRAM 102 that was earlier written by CPU 104. The data read from SDRAM 102 is then transmitted serially over USB link 128 by USB host controller 122. The serial engine on the external flash device can then accept the serial data and write the flash memory.
The inventors realize that buffering can improve data throughput. In particular, buffering of the data during the transfer between the flash-memory controller and the serial engine can improve throughput. The inventors also realize that a second data bus can further accelerate data transfers when the CPU does not use this second data bus. See for example Applicant's earlier patent, U.S. Pat. No. 6,874,044.
FIG. 4 shows a flash drive with a flash-serial buffer bus in parallel with the CPU bus with external and internal RAM buffers. CPU bus 38 inside flash drive controller chip 68 allows CPU 10 to access instructions in ROM 12, using master port 15 and slave port 11.
Master port 15 can also allow CPU 10 to write commands to flash-card controller 50 through its slave port 51, to flash-card controller 54 through its slave port 55, or to serial engine 32 through its slave port 35 connected to CPU bus 38. Flash-card controllers 50, 54 can access external RAM buffer 60 through their master ports 52, 56, over flash-serial buffer bus 40 and interface logic 64.
Likewise, serial engine 32 can use its master port 46 to access either slave port 42 of internal RAM buffer 34, or external RAM buffer 60 through interface logic 64. Other functional blocks may be integrated onto chip 68 besides flash-card controllers 50, 54 and may connect to CPU bus 38 or flash-serial buffer bus 40.
Once CPU 10 programs flash-card controllers 50, 54, or serial engine 32, data transfers can take place without using CPU bus 38. Data is sent over bus 40 to slave port 42 of RAM buffer 34. Once one or more blocks of flash data have been written into RAM buffer 34 by flash-card controller 50 or 54, serial engine 32 can read the flash data and serially transmit the flash data over USB link 18, uploading the data to a PC or other host device. Serial engine 32 uses its master port 46 to read the flash data in RAM buffer 34 using slave port 42.
While such flash readers are useful, the data stored on the flash-memory card may not be secure. The flash-memory card could be lost or stolen, especially for smaller-sized cards. The data on the card could be read by unauthorized persons, perhaps allowing that person to gain access to accounts or to sell valuable business or technical information. While data could be stored on the flash-memory card in an encrypted format using popular software programs, password-guessing programs could be used to guess the password and open the data for viewing.
What is desired is a secure flash-card reader that encrypts and decrypts data stored on flash-memory cards inserted into the secure flash-card reader. A secure flash-card reader is desired that operates with a secure host to ensure that unauthorized data access is blocked. A secure flash-card reader with a more advanced bus structures is desirable to increase the data transfer rates. Higher transfer rates within a secure flash-card reader are desirable. Tightly integrating hardware-based security features such as encryption engines within a secure flash-card reader with an advanced bus structure is desirable.